12,643 Lines of Code, GFX 13.0.1, and GFX 13.0.4: AMD Brings RDNA 5 GPU Support to the Linux Kernel Driver
The open-source software bring-up for AMD's next-generation graphics architecture has just reached a major engineering milestone. On Monday, November 9, 2026, Alex Deucher, AMD's lead maintainer for the open-source AMDGPU Linux kernel driver, published an extensive eight-patch series on the official Freedesktop.org amd-gfx mailing list introducing foundational support for the GFX13 (GC 13.x) graphics IP block that will power future AMD RDNA 5 GPUs.
In total, this initial kernel submission modifies 32 files across the drm/amdgpu and drm/amdkfd subsystems, adding 12,643 lines of new code (against just 15 deletions) before even accounting for the massive ASIC register header files that typically accompany a new Radeon silicon family.
GFX 13.0.1 and GFX 13.0.4: Inside the 8-Patch AMDGPU Linux Kernel Submission
Within AMD's internal engineering nomenclature, each major Graphics Core (GC) generation maps directly to a distinct GPU architecture: GFX10 powered RDNA 1 and RDNA 2, GFX11 drove RDNA 3 and RDNA 3.5, and GFX12 underpins the current RDNA 4 lineup led by the Radeon RX 9070 XT. The arrival of GFX13 code in the mainline kernel driver officially kicks off the kernel-level hardware bring-up for RDNA 5, laying the groundwork ahead of AMD's broader RDNA 5 and RDNA 5+ GPU architecture roadmap.
A closer inspection of the hardware discovery table in amdgpu_discovery.c reveals two specific silicon targets wired up in this first pull: GFX 13.0.1 (IP_VERSION(13, 0, 1)) and GFX 13.0.4 (IP_VERSION(13, 0, 4)). Enabling both IP revisions right out of the gate confirms that AMD's silicon teams are concurrently bringing up at least two distinct RDNA 5 hardware variants that share the soc_v2_0 common block and the GMC 13.0 (gmc_v13_0) graphics memory controller.
| Patch | AMD Engineer | Key Files & Scale | Technical Role |
|---|---|---|---|
| 1/8 | Frank Min | imu_v13_0.c (+319 lines) | Adds the IMU v13 (Integrated Management Unit) IP block for low-level GPU power and firmware management |
| 2/8 | Frank Min | gfx_v13_0.c (+5,808 lines) | Core implementation of the GFX v13.0 graphics and compute engine, command rings, and RLC/CP microcode |
| 3/8 | Frank Min | mes_v13_0.c (+2,781 lines) | Introduces the MES v13.0 (Micro Engine Scheduler) hardware scheduler block and API definitions |
| 4/8 | David Belanger & Jay Cornwall | cwsr_trap_handler_gfx13.asm (+1,749 lines) | Assembly CWSR (Compute Wave Save and Restore) trap handler for GFX13 compute preemption |
| 5/8 | David Belanger | amdgpu_amdkfd_gfx_v13.c (+1,122 lines) | Initial GC 13 bring-up in the AMDKFD (ROCm) compute driver and v13 MQD queue managers |
| 6/8 | Eric Huang | kfd_topology.c (+5 lines) | Disables queue reset in KFD topology for GFX13 hardware |
| 7/8 | Frank Min | amdgpu_discovery.c (+22 lines) | Enables the GFX 13.0.4 hardware target alongside GFX 13.0.1 |
| 8/8 | Kevin Wang | soc_v2_0.c (+3 lines) | Enables MGCG, CGCG, and CGLS clock gating power-saving features for GFX13 |
MES v13 Scheduler, IMU v13 Power Control, and ROCm Compute Plumbing Under the Hood
At the heart of the submission is gfx_v13_0.c, authored by AMD engineer Frank Min. Spanning 5,808 lines of code on its own (alongside clearstate_gfx13.h and the gc_13_0_1_sh_mask.h register masks), this core module establishes graphics and compute ring initialization, Command Processor (CP) microcode loading, RunList Controller (RLC) setup, and buffer state management for the GFX13 engine.
Equally important is the addition of the MES v13.0 (Micro Engine Scheduler) block across mes_v13_0.c (1,862 lines) and mes_v13_api_def.h (890 lines). The hardware scheduler handles low-level queue management and user-mode queue submissions, a critical pillar in AMD's ongoing push to cut CPU submission overhead in modern DirectX 12 and Vulkan titles running through Proton. Meanwhile, Jay Cornwall and David Belanger contributed 1,181 lines of assembly in cwsr_trap_handler_gfx13.asm to wire up Compute Wave Save and Restore (CWSR) preemption for the AMDKFD / ROCm compute stack, while Kevin Wang enabled Medium Grain Clock Gating (MGCG), Coarse Grain Clock Gating (CGCG), and Coarse Grain Light Sleep (CGLS) in soc_v2_0.c for both GFX 13.0.1 and GFX 13.0.4.
Targeting the Linux 7.5 Kernel Ahead of Future Radeon RX Hardware
Today's 12,643-line kernel drop connects the dots across several open-source components AMD has been quietly staging throughout 2026. Earlier this year, initial GFX13 targets (including gfx1310) landed in the LLVM 23 compiler back-end to establish instruction set generation. Over the summer, AMD engineers followed up by submitting initial patches for the Display Core Next 6 (DCN 6.0.0) display engine, explicitly linking it to GFX 13.0.1 with new plane scaling linearity and 4:2:0/4:2:2 chroma pre-scalers, alongside updates for the GMC 13.0 memory controller, SDMA 8.x DMA engines, and IH 8.0 interrupt handlers.
Given their publication in early November 2026 after the Linux 7.4 merge window closed, these baseline GFX13 patches are lined up to merge into the upcoming Linux 7.5 kernel cycle in early 2027. Upstreaming core kernel and ROCm plumbing well ahead of retail silicon is standard practice at AMD, ensuring that desktop Linux distributions and SteamOS devices enjoy stable day-one support when RDNA 5 consumer graphics cards arrive from 2027 onward. In the meantime, AMD's current RDNA 4 flagship, the Radeon RX 9070 XT (16GB GDDR6), continues to anchor the desktop lineup around the $920 mark at US retailers this November.
AMD Radeon RX 9070 XT (16GB GDDR6)
- AMD RDNA 4 Architecture (Navi 48)
- 16GB GDDR6 Memory on 256-bit Bus
- Full Support for AMD FSR 4 & AFMF 3
- Best-in-Class 1440p and 4K Value
My Field Notes
When Alex Deucher's team drops more than 12,600 lines of C and assembly code onto the mailing list in a single afternoon, it is a clear sign that lab bring-up on early RDNA 5 silicon is moving at full speed. Right now, both gfx_v13_0.c and the KFD compute layer intentionally lean on a GFX12-derived template to get the core rings booting cleanly without tipping AMD's hand on unannounced shader capabilities. Still, as Chayane pointed out while we were looking over the mes_v13_0.c hardware scheduler and the cwsr_trap_handler_gfx13.asm preemption code, the upcoming Mesa RADV Vulkan patches and shader ISA updates will be the real place to watch for RDNA 5's next-generation ray tracing and matrix acceleration upgrades beyond FSR 4.
Seeing AMD wire up two separate targets (GFX 13.0.1 and GFX 13.0.4) with working MGCG and CGCG clock gating in time for the Linux 7.5 kernel bodes very well for open-source driver maturity. We have not yet had a physical unit on our desk, so if the manufacturer's team would like to send over a review sample so we can put it through our full real-world testing protocol, our lab doors are wide open.
PC hardware enthusiast and competitive gamer, Arthur 'Heimdall' splits his time between France and the UK working in enterprise B2B software solutions. A business school graduate passionate about component benchmarking, he has been building, modding, and tuning PCs since childhood, optimizing every thermal degree and millisecond of display latency. An avid gamer across Assassin's Creed and sandbox titles, he forged his alliance with Grimtag and Chaya during late-night World of Warcraft raids before joining Pro-Gamer.
