192 Zen 6 Cores, SOCAMM2 Memory, and 50% Less DDR5: How AMD Is Tackling the RAM Crisis with Verano and MEXT
The data center battlefield has just taken a highly practical turn for the entire hardware industry. During its latest technical briefing dedicated to the sixth-generation AMD EPYC 9006 server processor lineup, the Santa Clara chipmaker pulled back the curtain on its new TSMC 2nm Zen 6 architecture, headlined by a specialized low-power family codenamed EPYC 9006 LP "Verano". Even more importantly, AMD engineers introduced two crucial weapons designed to ease the global memory shortage: modular LPDDR5X SOCAMM2 memory support and the MEXT memory extension technology, which can slash server DDR5 capacity requirements by 50% without sacrificing throughput.
Venice, Verano, and the SB1 Socket: Up to 192 Zen 6 Cores and 24-Channel LPDDR5X
The EPYC 9006 ecosystem now spans three distinct hardware platforms engineered to cover every tier of modern compute. At the top of the stack, standard Venice processors sit on the SP7 and SP8 sockets, scaling up to 256 Zen 6c cores (512 threads) alongside a 16-channel DDR5 and MRDIMM memory subsystem. Meanwhile, the industrial EPYC Embedded 9006 series on the SP7 platform brings a seven-year longevity guarantee and a claimed 1.8x to 2.0x performance uplift over previous-generation EPYC chips, maintaining the company's relentless engineering pace right after AMD's RDNA 5 GPU architecture deployment inside the Linux kernel driver.
However, the standout architectural shift lies in Verano. Branded as the EPYC 9006 LP (Low Power) series and inaugurating a purpose-built physical socket named SB1, these processors are engineered as power-efficient host orchestrators built to keep dense racks of AI accelerators fed, including AMD Instinct GPUs and Google's new TPU v8 family. Under the hood, Verano packs up to 6 Zen 6 CCDs for a maximum configuration of 192 cores, alongside 72-core variants capable of reaching a 5.0 GHz boost clock. The math reveals a major milestone: each Zen 6 CCD now houses up to 32 physical cores on a single chiplet die, doubling or quadrupling the 8-core and 16-core CCD layouts of previous generations.
To feed up to 192 cores without blowing past rack thermal limits or consuming mountains of traditional server DIMMs, the SB1 platform drops standard DDR5 in favor of low-power LPDDR5X memory. Delivered via replaceable SOCAMM2 (System-on-Chip Advanced Memory Module 2) form-factor modules, Verano unlocks an expansive 24-channel LPDDR5X memory subsystem that maximizes bandwidth per watt.
AMD MEXT: Predictive Flash Tiering That Cuts DDR5 Requirements by 50%
In late 2026, skyrocketing DRAM prices are squeezing cloud hyperscalers and PC builders alike, as memory foundries aggressively reallocate wafer capacity toward HBM4 stacks for AI accelerators. Against this backdrop of acute supply pressure, which recently sparked Elon Musk's Terafab project targeting 700,000 DRAM memory wafers per month, AMD is rolling out its hardware-and-software answer called MEXT (Memory Extension).
Born from AMD's acquisition of memory startup Mext, this predictive memory tiering solution pairs a low-overhead Linux kernel driver with a lightweight, Transformer-derived predictive AI model. Instead of forcing every gigabyte of an application's working set to sit permanently inside expensive DRAM sticks, MEXT predicts memory access patterns ahead of time and transparently tiers data pages between physical DDR5 DRAM and high-speed NVMe / NAND Flash storage.
| AMD Platform / Technology | Socket & Architecture | Core Configuration | Memory Subsystem & Impact |
|---|---|---|---|
| EPYC 9006 "Venice" | SP7 / SP8 Sockets (2nm Zen 6 / Zen 6c) | Up to 256 cores / 512 threads | 16-channel DDR5 / MRDIMM (up to 2.0x uplift on Embedded series) |
| EPYC 9006 LP "Verano" | Low-power SB1 Socket (2nm Zen 6) | Up to 192 cores (6x 32-core CCDs, up to 5.0 GHz boost) | 24-channel LPDDR5X via replaceable SOCAMM2 modules |
| AMD MEXT Solution | Linux Kernel Driver + Predictive Tiering | Supported across EPYC 9006 lineup | DRAM + Flash tiering cutting physical DDR5 footprint by 50% (and up to 75%) |
The benchmark figures shared by AMD during its presentation are striking: across memory-bound workloads such as electronic design automation (EDA), large-scale databases, and AI pipelines, an EPYC server running MEXT retains nearly identical performance while cutting physical DDR5 capacity by 50% (with total DRAM savings ranging from 20% to 75% depending on the workload). Hardware acquisition costs drop substantially, and the relentless pressure exerted by data centers on global DDR5 supply chains gets an immediate release valve.
"We Didn't Magically Know Four Years Ago": Mike Clark Calls Out Nvidia and Arm
Beyond raw silicon metrics, AMD's briefing stood out for its refreshingly candid pushback against the marketing buzzwords currently flooding the server industry. Over recent months, both Nvidia (with its Vera CPU) and Arm have repeatedly claimed that their latest data center processors were purpose-built from the ground up specifically for "agentic AI" (autonomous software agents capable of chaining multi-step tasks, executing code, and querying databases). During the session, Corporate VP of Server Products Madhu Rangarajan, Server Business SVP Dan McNamara, and Chief Zen Architect Mike Clark dismantled that narrative head-on.
"We think that the EPYC 9006 CPU is the best CPU for the agentic era, and spoiler alert, we didn't magically know four years ago that agentic was going to be a thing and purpose-built something for agentic."
Backing up Rangarajan's blunt assessment, Mike Clark pointed out an unshakeable engineering reality: designing a new CPU microarchitecture from scratch takes four years. When AMD's silicon architects locked in the foundational design goals for Zen 6 back in 2022, the concept of agentic AI simply did not exist on any industry roadmap. According to Clark, claiming otherwise is pure revisionist marketing: the reason EPYC 9006 excels at unpredictable, branch-heavy agentic workloads today is that AMD built a versatile, general-purpose x86 architecture with massive IPC gains, deep caches, and low-latency memory access rather than chasing a single software buzzword.
The Strategist's Take
You have to appreciate Mike Clark and the AMD server team's candor here: hearing the father of the Zen architecture publicly call out competitors for pretending they designed transistors in 2022 for a software trend that only emerged recently is a breath of fresh air in an industry drowning in buzzwords. As a PC hardware enthusiast, two concrete takeaways jump right off this spec sheet. First, seeing 2nm Zen 6 CCDs scale up to 32 cores per chiplet has huge implications for future desktop Ryzen processors on the AM5 socket: packing 16 or 24 cores onto a single CCD without any cross-chiplet latency penalty in games promises a massive generational leap. Second, pairing replaceable LPDDR5X SOCAMM2 modules with MEXT Flash tiering is easily the best news of the year for PC gamers' wallets: if hyperscale data centers finally cut their DDR5 consumption in half, the relentless price surge on consumer desktop RAM might finally hit a ceiling. We have not yet had a physical unit on our desk,if the manufacturer's team would like to send over a review sample so we can put it through our full real-world testing protocol, our lab doors are wide open.
Born and based in Montreal's Mile End district, Maëlle "Kaelen" became close friends with Chaya during their university software engineering years, bonding over late-night coding labs, campus LANs, and World of Warcraft raids alongside Grimtag and Heimdall. A game systems balancing consultant and lifelong theorycrafter, she cut her teeth in the early 2010s writing boss walkthroughs, frame-data breakdowns, and competitive meta guides for specialized French-language MMORPG and esports portals, including Mondes Persistants, as well as North American strategy collections. On Pro-Gamer, she leads in-depth walkthroughs, build optimization, and tactical esports coverage.
