AMD Ryzen Zen 6 "Medusa" APUs: GPUOpen's HIPRT 3.2 Ray-Tracing Update Confirms RDNA 4m and RDNA 3.5 GPUs
Nine months after shipping version 3.1 in January, AMD's graphics software engineers have published the major HIPRT 3.2.0 release on the official GPUOpen GitHub repository. Beyond optimizing bounding volume hierarchy (BVH) traversal and ray intersection kernels, the updated C++ codebase officially lays the groundwork for next-generation AMD Ryzen Zen 6 "Medusa" APUs.
Both the official release notes and the bitcode compilation scripts explicitly introduce three new hardware targets grouped under the Medusa codename: gfx1170, gfx1171, and gfx115E. Together, these identifiers confirm how AMD plans to divide its integrated GPU architectures across future laptops, mini-PCs, and handheld gaming systems.
RDNA 4m (gfx1170, gfx1171) and RDNA 3.5 (gfx115E): A Two-Tiered Integrated Graphics Lineup
Inside the Clang target validation list of the HIP SDK, AMD maps the upcoming Zen 6 Medusa processor family across two distinct graphics branches. The gfx1170 and gfx1171 device IDs belong to the RDNA 4m family, whereas gfx115E sits directly within the RDNA 3.5 lineage alongside existing Strix Point (gfx1150/gfx1151) and Krackan (gfx1152/gfx1153) silicon.
Pairing both architectures under the Medusa umbrella points to a segmented silicon strategy, building on the approach seen with the 8-core Ryzen AI 7 HX 455 and its full 16-CU Radeon 890M iGPU. Mainstream monolithic Medusa Point designs can rely on a refined RDNA 3.5 block (denoted by the hexadecimal E stepping), while higher-tier configurations step up to RDNA 4m compute units equipped with upgraded matrix math capabilities.
Check Availability AMD Ryzen Processors and Laptops Availability on Amazon→
Inside the C++ Source Code: RTIP 2.0 Hardware Level and the gfx115E Hexadecimal Fix
Inspecting Context.cpp within AMD's official HIP Ray Tracing library reveals a crucial architectural detail about how these integrated GPUs handle hardware-accelerated ray tracing. Inside the Context::getRtip() hardware detection routine, every architecture ID between 0x1100 and 0x11FF is assigned to RTIP 2.0 (Ray Tracing IP level 2.0).
Because gfx1170, gfx1171, and gfx115E all remain under the 0x1200 threshold, Medusa's integrated GPUs retain a 4-wide BVH branching factor rather than the 8-wide RTIP 3.1 engine and post-loop triangle normal decoding reserved for desktop RDNA 4 cards (gfx1200 and gfx1201). Keeping RDNA 4m rooted in the GFX11 hierarchy confirms that it is a targeted mobile evolution grafting matrix instructions (WMMA and FP8/BF8 formats) onto a proven foundation, complementing AMD's rollout of FSR 4.1 across Radeon GPUs and Ryzen APUs via Vulkan.
Adding the gfx115E target also forced AMD engineers to fix a subtle parsing bug in the runtime context initializer. Previous versions parsed the digits after gfx in base 10 using std::stoi, which halted at the letter E and truncated gfx115E to 115, breaking wave32 lane-mask detection until the parser was switched to hexadecimal (base 16).
Breaking API 3002 Changes, SRT Shear Transforms, and CUDA 13 Support
Alongside Zen 6 Medusa enablement, HIPRT 3.2.0 bumps HIPRT API VERSION to 3002 and introduces several low-level upgrades that require 3D rendering engines like Blender Cycles to be recompiled:
- Expanded 64-byte SRT Frames (
hiprtFrameSRT): A newshearfield has been inserted between scale and translation, growing the structure from 48 to 64 bytes (with 64-byte alignment) and rejecting legacy 3.1 binaries at context creation to prevent memory corruption. - Device-Side Instance Transform Queries: Shaders and compute kernels can now read back object-to-world and world-to-object matrices directly from GPU device code across both two-level and multi-level (MLAS) BVH hierarchies.
- CUDA 13 Compatibility and Windows SDK Priority: Bundled
hipRTCandcomgrDLLs move from version 6.4 to 7.1 (with support forhipRTC 7.8+), cross-platform compilation adds CUDA 13 support, and Windows builds now prioritize the developer's SDK path over older driver DLLs stored inSystem32.
My Test Bench: Why Keeping the RTIP 2.0 Engine on Medusa Calls for Realistic Expectations
Looking closely at the hardware routing table inside Context.cpp, the most telling detail to me is seeing gfx1170 and gfx1171 stay below the 0x1200 cutoff. Even on Zen 6 Medusa configurations equipped with the newer RDNA 4m graphics block, ray traversal still runs on the 4-wide RTIP 2.0 intersection engine rather than the 8-wide RTIP 3.1 hardware blocks built into desktop Radeon RX 9070 cards.
Within a tight 15W to 54W mobile power envelope, however, that silicon trade-off makes complete engineering sense. Doubling the BVH node footprint in hardware eats up valuable die area on an APU, whereas adding dedicated FP8 matrix math instructions to a mature GFX11 pipeline delivers the AI upscaling throughput portable gaming laptops and handhelds actually need first.
PC hardware enthusiast and competitive gamer, Arthur 'Heimdall' splits his time between France and the UK working in enterprise B2B software solutions. A business school graduate passionate about component benchmarking, he has been building, modding, and tuning PCs since childhood, optimizing every thermal degree and millisecond of display latency. An avid gamer across Assassin's Creed and sandbox titles, he forged his alliance with Grimtag and Chaya during late-night World of Warcraft raids before joining Pro-Gamer.
